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Enumerating floorplans with n roomsNAKANO, Shin-Ichi.Lecture notes in computer science. 2001, pp 107-115, issn 0302-9743, isbn 3-540-42985-9Conference Paper

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Canonical decomposition, realizer, Schnyder labeling and orderly spanning trees of plane graphs: (Extended abstract)MIURA, Kazuyuki; AZUMA, Machiko; NISHIZEKI, Takao et al.Lecture notes in computer science. 2004, pp 309-318, issn 0302-9743, isbn 3-540-22856-X, 10 p.Conference Paper

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Placing, routing, and editing virtual FPGAsLAGADEC, Loïc; LAVENIER, Dominique; FABIANI, Erwan et al.Lecture notes in computer science. 2001, pp 357-366, issn 0302-9743, isbn 3-540-42499-7Conference Paper

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A logic-to-logic comparator for VLSI layout verificationMAURER, P. M; SCHAPIRA, A. D.IEEE transactions on computer-aided design of integrated circuits and systems. 1988, Vol 7, Num 8, pp 897-907, issn 0278-0070Article

Linear placement algorithms and applications to VLSI designCHUNG-KUAN CHENG.Networks (New York, NY). 1987, Vol 17, Num 4, pp 439-464, issn 0028-3045Article

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Construction plan of Tohoku through lineKOBAYASHI, Chika.Japanese railway engineering. 2009, Vol 49, Num 1, issn 0448-8938, a, 11-13 [4 p.]Article

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